mirror of https://github.com/YosysHQ/yosys.git
66 lines
2.4 KiB
Plaintext
66 lines
2.4 KiB
Plaintext
design -reset
|
|
read_verilog <<EOT
|
|
module top(input a, input b, input sel, output y);
|
|
assign y = sel ? a : b;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +3/ +1" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
|
|
logger -expect error "Found 1 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input [3:0] data, input [1:0] sel, output y);
|
|
assign y = data[sel];
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +6/ +1" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
|
|
logger -expect error "Found 1 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input a, input b, input c, input s1, input s2, output y);
|
|
wire temp;
|
|
assign temp = s1 ? a : b;
|
|
assign y = s2 ? temp : c;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +5/ +1" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
|
|
logger -expect error "Found 1 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input [2:0] a, output [1:0] y);
|
|
assign y = a[2] ? 2'b11 : a[1] ? 2'b10 : a[0] ? 2'b01 : 2'b00;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +3/ +2" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 2
|
|
logger -expect error "Found 2 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|