diff --git a/techlibs/fabulous/CMakeLists.txt b/techlibs/fabulous/CMakeLists.txt
index f1825cd4f..0a658e322 100644
--- a/techlibs/fabulous/CMakeLists.txt
+++ b/techlibs/fabulous/CMakeLists.txt
@@ -31,4 +31,5 @@ yosys_pass(synth_fabulous
 	DATA_DIR
 		fabulous
 	DATA_FILES
+		cells_bb.v
 )
diff --git a/techlibs/fabulous/cells_bb.v b/techlibs/fabulous/cells_bb.v
new file mode 100644
index 000000000..8ca768eaf
--- /dev/null
+++ b/techlibs/fabulous/cells_bb.v
@@ -0,0 +1,18 @@
+// Pad cells inserted by synth_fabulous via iopadmap.
+// Mapped to fabric primitives by a user supplied -extra-map.
+
+(* blackbox *)
+module \$__FABULOUS_IBUF (input PAD, output OUT);
+endmodule
+
+(* blackbox *)
+module \$__FABULOUS_OBUF (output PAD, input IN);
+endmodule
+
+(* blackbox *)
+module \$__FABULOUS_TBUF (output PAD, input IN, input EN);
+endmodule
+
+(* blackbox *)
+module \$__FABULOUS_IOBUF (inout PAD, output OUT, input IN, input EN);
+endmodule
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
index e4a83ae15..2e5fbd104 100644
--- a/techlibs/fabulous/synth_fabulous.cc
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -274,6 +274,7 @@ struct SynthPass : public ScriptPass {
 
 	void script() override
 	{
+		run("read_verilog -icells -lib +/fabulous/cells_bb.v");
 		if (help_mode) {
 			run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
 		} else