From 72b30b182008fadc8ff87083d0b4c23c648574ff Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 14 Sep 2026 12:51:34 +0200 Subject: [PATCH] abc: dispatch modules in cell count order Co-authored-by: Jakub Michalski --- passes/techmap/abc.cc | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index bbcbbbcda..9ea843f2a 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -2411,13 +2411,21 @@ struct AbcPass : public Pass { std::exception_ptr error; try { - for (auto mod : design->selected_modules()) - { - if (mod->processes.size() > 0) { + // Process modules from the largest to the smallest. This improves + // the runtime when module sizes are varied, by avoiding the case + // where some large module is picked last + std::vector sorted_modules; + for (auto mod : design->selected_modules()) { + if (mod->processes.empty()) + sorted_modules.push_back(mod); + else log("Skipping module %s as it contains processes.\n", mod); - continue; - } + } + std::stable_sort(sorted_modules.begin(), sorted_modules.end(), + [](RTLIL::Module *a, RTLIL::Module *b) { return GetSize(a->cells_) > GetSize(b->cells_); }); + for (auto mod : sorted_modules) + { std::shared_ptr module_data = std::make_shared(); module_data->module = mod; AbcSigMap &assign_map = module_data->assign_map;