rtlil: add module assertion to RewriteSigSpecWorker

This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:47:43 +02:00
parent b4d8b074cb
commit 692fcdfc5b
+4 -1
View File
@@ -2644,17 +2644,20 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
struct RewriteSigSpecWorker
{
const dict<RTLIL::Wire*, RTLIL::Wire*> &wire_map;
const RTLIL::Module *new_mod;
void operator()(RTLIL::SigSpec &sig)
{
sig.rewrite_wires([this](RTLIL::Wire *&wire) {
auto it = wire_map.find(wire);
if (it != wire_map.end())
wire = it->second;
else
log_assert(wire->module == new_mod);
});
}
};
RewriteSigSpecWorker rewriteSigSpecWorker{wire_map};
RewriteSigSpecWorker rewriteSigSpecWorker{wire_map, new_mod};
new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
new_mod->fixup_ports();
}