From 692fcdfc5b8f5b3f6636147014dc072612995e88 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 2 Oct 2026 18:47:43 +0200
Subject: [PATCH] rtlil: add module assertion to RewriteSigSpecWorker

---
 kernel/rtlil.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d00139130..e2c59c301 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2644,17 +2644,20 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 	struct RewriteSigSpecWorker
 	{
 		const dict<RTLIL::Wire*, RTLIL::Wire*> &wire_map;
+		const RTLIL::Module *new_mod;
 		void operator()(RTLIL::SigSpec &sig)
 		{
 			sig.rewrite_wires([this](RTLIL::Wire *&wire) {
 				auto it = wire_map.find(wire);
 				if (it != wire_map.end())
 					wire = it->second;
+				else
+					log_assert(wire->module == new_mod);
 			});
 		}
 	};
 
-	RewriteSigSpecWorker rewriteSigSpecWorker{wire_map};
+	RewriteSigSpecWorker rewriteSigSpecWorker{wire_map, new_mod};
 	new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
 	new_mod->fixup_ports();
 }