mirror of https://github.com/YosysHQ/yosys.git
57 lines
1.4 KiB
Plaintext
57 lines
1.4 KiB
Plaintext
pattern negexpand
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//
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// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
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//
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// Expand negation over addition
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//
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// -(a + b) ===> (-a) + (-b)
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//
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state <SigSpec> neg_a neg_y add_a add_b
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state <bool> a_signed
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match neg
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select neg->type == $neg
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set neg_a port(neg, \A)
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set neg_y port(neg, \Y)
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set a_signed neg->getParam(\A_SIGNED).as_bool()
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endmatch
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match add
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select add->type == $add
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index <SigSpec> port(add, \Y) === neg_a
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select nusers(port(add, \Y)) == 2
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set add_a port(add, \A)
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set add_b port(add, \B)
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endmatch
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code neg_a neg_y add_a add_b a_signed
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if (add->getParam(\A_SIGNED).as_bool() != a_signed)
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reject;
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if (add->getParam(\B_SIGNED).as_bool() != a_signed)
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reject;
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{
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// Use output width for negations to handle overflow correctly
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int width = GetSize(neg_y);
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SigSpec neg_add_a = module->addWire(NEW_ID, width);
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Cell *neg_a_cell = module->addNeg(NEW_ID, add_a, neg_add_a, a_signed);
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SigSpec neg_add_b = module->addWire(NEW_ID, width);
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Cell *neg_b_cell = module->addNeg(NEW_ID, add_b, neg_add_b, a_signed);
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Cell *new_add = module->addAdd(NEW_ID, neg_add_a, neg_add_b, neg_y, a_signed);
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log("negexpand pattern in %s: neg=%s, add=%s\n",
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log_id(module), log_id(neg), log_id(add));
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neg_a_cell->fixup_parameters();
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neg_b_cell->fixup_parameters();
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new_add->fixup_parameters();
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autoremove(neg);
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autoremove(add);
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did_something = true;
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}
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accept;
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endcode
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