From 3f00e570762a87cfec8a5e672c4375f56cfe636a Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Mon, 31 Mar 2025 01:22:42 -0700 Subject: [PATCH] Improve the naming for opt_reduce --- passes/opt/opt_reduce.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index d27878fa7..323e7b6fb 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -128,13 +128,14 @@ struct OptReduceWorker if (this_s.size() > 1) { - RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or)); + RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID2_SUFFIX("reduce_or"), ID($reduce_or)); // SILIMATE: Improve the naming reduce_or_cell->setPort(ID::A, this_s); reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); + reduce_or_cell->set_src_attribute(cell->get_src_attribute()); // SILIMATE: Improve the naming - RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); + RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID2_SUFFIX("reduce_or_wire")); // SILIMATE: Improve the naming this_s = RTLIL::SigSpec(reduce_or_wire); reduce_or_cell->setPort(ID::Y, this_s); }