fix $specrule port naming

abc

@@ -1 +1 @@
-Subproject commit 180a6adb68e855942e859f3646eff7762c7bc3e6
+Subproject commit 8827bafb7f288de6749dc6e30fa452f2040949c0

kernel/celltypes.h

@@ -103,7 +103,7 @@ struct CellTypes
 		setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y});
 		setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
 		setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>());
-		setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
+		setup_type(ID($specrule), {ID::SRC_EN, ID::DST_EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
 		setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
 		setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
 		setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});

kernel/constids.inc

@@ -459,9 +459,7 @@ X(EDGE_POL)
 X(EFX_ADD)
 X(EN)
 X(ENPOL)
-X(EN_DST)
 X(EN_POLARITY)
-X(EN_SRC)
 X(EQN)
 X(F)
 X(FDCE)

techlibs/common/simlib.v

@@ -1976,7 +1976,7 @@ endmodule
 // --------------------------------------------------------
 //* group spec
 
-module \$specrule (EN_SRC, EN_DST, SRC, DST);
+module \$specrule (SRC_EN, DST_EN, SRC, DST);
 
 parameter TYPE = "";
 parameter T_LIMIT = 0;
@@ -1991,7 +1991,7 @@ parameter SRC_POL = 0;
 parameter DST_PEN = 0;
 parameter DST_POL = 0;
 
-input EN_SRC, EN_DST;
+input SRC_EN, DST_EN;
 input [SRC_WIDTH-1:0] SRC;
 input [DST_WIDTH-1:0] DST;
 

tests/functional/rtlil_cells.py

@@ -337,7 +337,7 @@ rtlil_cells = [
 #    ("tribuf", ["A", "EN", "Y"]),
 #    ("specify2", ["EN", "SRC", "DST"]),
 #    ("specify3", ["EN", "SRC", "DST", "DAT"]),
-#    ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]),
+#    ("specrule", ["SRC_EN", "DST_EN", "SRC", "DST"]),
     BWCell("bweqx", [10, 16, 40]),
     BWCell("bwmux", [10, 16, 40]),
     FFCell("ff", [10, 20, 40]),