From 3b64de37629f42841a1f9c6b98ce09fd6998f953 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 13 Apr 2026 16:48:27 +0200
Subject: [PATCH] fix $specrule port naming

---
 abc                             | 2 +-
 kernel/celltypes.h              | 2 +-
 kernel/constids.inc             | 2 --
 techlibs/common/simlib.v        | 4 ++--
 tests/functional/rtlil_cells.py | 2 +-
 5 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/abc b/abc
index 180a6adb6..8827bafb7 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit 180a6adb68e855942e859f3646eff7762c7bc3e6
+Subproject commit 8827bafb7f288de6749dc6e30fa452f2040949c0
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 50dee573e..ceff0bd1a 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -103,7 +103,7 @@ struct CellTypes
 		setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y});
 		setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
 		setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>());
-		setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
+		setup_type(ID($specrule), {ID::SRC_EN, ID::DST_EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
 		setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
 		setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
 		setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
diff --git a/kernel/constids.inc b/kernel/constids.inc
index c99aa788d..61c9b3a8c 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -459,9 +459,7 @@ X(EDGE_POL)
 X(EFX_ADD)
 X(EN)
 X(ENPOL)
-X(EN_DST)
 X(EN_POLARITY)
-X(EN_SRC)
 X(EQN)
 X(F)
 X(FDCE)
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e0fb9fbfa..3f34bfd22 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1976,7 +1976,7 @@ endmodule
 // --------------------------------------------------------
 //* group spec
 
-module \$specrule (EN_SRC, EN_DST, SRC, DST);
+module \$specrule (SRC_EN, DST_EN, SRC, DST);
 
 parameter TYPE = "";
 parameter T_LIMIT = 0;
@@ -1991,7 +1991,7 @@ parameter SRC_POL = 0;
 parameter DST_PEN = 0;
 parameter DST_POL = 0;
 
-input EN_SRC, EN_DST;
+input SRC_EN, DST_EN;
 input [SRC_WIDTH-1:0] SRC;
 input [DST_WIDTH-1:0] DST;
 
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index 964d81ddf..9a44821d3 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -337,7 +337,7 @@ rtlil_cells = [
 #    ("tribuf", ["A", "EN", "Y"]),
 #    ("specify2", ["EN", "SRC", "DST"]),
 #    ("specify3", ["EN", "SRC", "DST", "DAT"]),
-#    ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]),
+#    ("specrule", ["SRC_EN", "DST_EN", "SRC", "DST"]),
     BWCell("bweqx", [10, 16, 40]),
     BWCell("bwmux", [10, 16, 40]),
     FFCell("ff", [10, 20, 40]),