From 2ccfd2b23beefed7629f0e97e96c1067ebd14f8f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Mar 2026 12:25:37 +0100 Subject: [PATCH] synth_ice40: always read abc9 model to understand port direction --- techlibs/ice40/synth_ice40.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 30c331e17..d907f662d 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -360,6 +360,7 @@ struct SynthIce40Pass : public ScriptPass run("techmap"); else { run("ice40_wrapcarry"); + run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v"); run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); } run("opt -fast"); @@ -389,7 +390,6 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); } if (!noabc) { - run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v"); std::string abc9_opts; std::string k = "synth_ice40.abc9.W"; if (active_design && active_design->scratchpad.count(k))