diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc
index a2fd53d68..f4eeeb9c9 100644
--- a/backends/aiger2/aiger.cc
+++ b/backends/aiger2/aiger.cc
@@ -1430,7 +1430,7 @@ struct XAigerWriter : AigerWriter {
 							bit = conn[i];
 						} else {
 							// FIXME: hierarchical path
-							log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
+							log_debug("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
 										port_id.unescape(), i, box, box->type.unescape());
 							bit = RTLIL::Sx;
 						}
@@ -1466,7 +1466,7 @@ struct XAigerWriter : AigerWriter {
 							bit = conn[i];
 						} else {
 							// FIXME: hierarchical path
-							log_warning("connection on port %s[%d] of instance %s (type %s) missing\n",
+							log_debug("connection on port %s[%d] of instance %s (type %s) missing\n",
 										port_id.unescape(), i, box, box->type.unescape());
 							pad_pi();
 							continue;
diff --git a/tests/arch/xilinx/dsp_abc9.ys b/tests/arch/xilinx/dsp_abc9.ys
index 034948d1d..ceabefca1 100644
--- a/tests/arch/xilinx/dsp_abc9.ys
+++ b/tests/arch/xilinx/dsp_abc9.ys
@@ -1,5 +1,6 @@
 logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*"
 logger -nowarn "Ignoring boxed module .*\."
+logger -nowarn "Feature 'write_xaiger2' is experimental\."
 
 read_verilog <<EOT
 module top(input [24:0] A, input [17:0] B, output [47:0] P);