yosys/tests/verific/README.md

# Verific Test Cases

## Disabled

- `import_warning_operator`: no VHDL
- `mixed_flist`: no VHDL
- `memory_semantics`: relies on initial values being retained, which we do not want
- `rom_case`: we need different behavior for multi-port memories
- `blackbox*`: we need different behavior for parametrized blackboxes
- `chformal`: relies on initial values being retained, which we do not want
Clean up Verific tests 2024-09-23 13:05:08 +02:00			`# Verific Test Cases`

Standardize convention, add back test, update README 2024-09-23 15:06:43 +02:00			`## Disabled`
Clean up Verific tests 2024-09-23 13:05:08 +02:00
Switch back to main Verific without VHDL support 2026-02-19 06:57:14 +01:00			- `import_warning_operator`: no VHDL
			- `mixed_flist`: no VHDL
Update Verific README 2024-09-23 14:35:48 +02:00			- `memory_semantics`: relies on initial values being retained, which we do not want
Add back VHDL support 2025-10-02 09:39:33 +02:00			- `rom_case`: we need different behavior for multi-port memories
Disable Verific blackbox checks (different from our preferred approach) 2025-01-21 14:46:40 +01:00			- `blackbox*`: we need different behavior for parametrized blackboxes
Remove chformal test from verific since it requires initial value preservation 2025-07-22 03:07:49 +02:00			- `chformal`: relies on initial values being retained, which we do not want