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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers fddc4650d1 graphs will autoload (if autoload checked) raw data even if no raw file is specified in graph dialog box (use current loaded raw file, usually a different analysis) 2024-09-06 16:57:13 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin proc ev, ev0, to_eng: evaluate expr at global scope so global vars will be expanded correctly ($path) 2024-05-29 09:41:52 +02:00
doc fix escape recognition in translate3(), so in symbol texts it is possible to write \\@name to an instance attribute to get literal @name in displayed text instead of the instance name. fix typo in tutorial_use_existing_subckt.html. some schematic updates (no more enable show_pin_net_names tcl variable) 2024-08-28 09:39:43 +02:00
scconfig fix escape recognition in translate3(), so in symbol texts it is possible to write \\@name to an instance attribute to get literal @name in displayed text instead of the instance name. fix typo in tutorial_use_existing_subckt.html. some schematic updates (no more enable show_pin_net_names tcl variable) 2024-08-28 09:39:43 +02:00
src graphs will autoload (if autoload checked) raw data even if no raw file is specified in graph dialog box (use current loaded raw file, usually a different analysis) 2024-09-06 16:57:13 +02:00
tests update hash netlist value in xschemtest.tcl for rom8k.sch 2024-07-18 22:09:25 +02:00
xschem_library graphs will autoload (if autoload checked) raw data even if no raw file is specified in graph dialog box (use current loaded raw file, usually a different analysis) 2024-09-06 16:57:13 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog to 3.4.5 2024-05-28 16:46:26 +02:00
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Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions