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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik fd5e6caf13 preserve line ordering regardless of awk hash implementation in tedax netlists as done for vhdl and verilog; include a couple of tedax netlist checks in xschemtest 2021-12-16 00:39:09 +01:00
XSchemWin do not hash the comments containing absolute paths in xschemtest netlist check, since these vary on different systems 2021-12-14 12:40:32 +01:00
doc doc updates about menu text change 2021-12-01 15:03:10 +01:00
scconfig old_winpath[] removed from globals, put as static string into callback(), fix ngspice::annotate netlist_dir fetching. 2021-11-23 23:20:10 +01:00
src preserve line ordering regardless of awk hash implementation in tedax netlists as done for vhdl and verilog; include a couple of tedax netlist checks in xschemtest 2021-12-16 00:39:09 +01:00
tests preserve line ordering regardless of awk hash implementation in tedax netlists as done for vhdl and verilog; include a couple of tedax netlist checks in xschemtest 2021-12-16 00:39:09 +01:00
xschem_library preserve ordering in verilog/VHDL signal/wire/reg declarations for consistent netlist hashing/checking 2021-12-15 15:17:45 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions