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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers f2214150ae tedax, verilog, spice netlists: do not expand unused subcircuits (due to *_ignore attrs on instances/symbols) 2023-05-10 01:02:28 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin mosgen has been changed to mosgen.tcl 2023-05-08 23:15:58 +02:00
doc update docs about renamed generators (extension added) 2023-05-06 09:40:44 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src tedax, verilog, spice netlists: do not expand unused subcircuits (due to *_ignore attrs on instances/symbols) 2023-05-10 01:02:28 +02:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library symbol_ignore=true attribute can be set on all symbol elements (text, lines, rectangles, arcs, polys, instances, nets) such that these marked elements are not displayed when symbol is instantiated. 2023-05-09 23:26:46 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions