A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Go to file
Stefan Frederik ed0924e6ca drill_hilight(): propagate only selected bits of bus nets 2022-10-29 11:06:46 +02:00
XSchemWin add option add_all_windows_drives 2022-10-28 08:54:52 +02:00
doc add documentation files 2022-10-26 19:46:36 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src drill_hilight(): propagate only selected bits of bus nets 2022-10-29 11:06:46 +02:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library update test schematic (better screen redraw if moving while simulating) 2022-10-27 10:09:19 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions