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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers e999a13c8d doc updates (graphs) 2023-02-10 18:42:11 +01:00
XSchemWin put a typedef in xschem.h to avoid duplicate declarations. add env tcl to global list in proc simulate 2023-02-06 14:36:24 +01:00
doc doc updates (graphs) 2023-02-10 18:42:11 +01:00
scconfig set fatal flag in require() for type checks 2023-01-25 11:45:33 +01:00
src better xschem table_read command implementation 2023-02-10 18:08:45 +01:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library rename top_subckt to lvs_netlist (more appropriate), better tcp interface (redirect stdout to socket in addition to command return value) 2023-02-09 11:30:27 +01:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions