A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Go to file
stefan schippers e948edbffa descend_schematic(): vectorize #netxxx nets if connected to bussed pins, before hashing, so resolved_net(...) will return the correct net portmapping 2023-06-01 06:40:24 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin fix some errors found by Joanne in test_bus_tap.sch 2023-05-31 00:14:22 +02:00
doc add net_name=true in bus_tap.sym (so avoid setting it on instancs), add documentation for bus taps 2023-05-30 11:03:07 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src descend_schematic(): vectorize #netxxx nets if connected to bussed pins, before hashing, so resolved_net(...) will return the correct net portmapping 2023-06-01 06:40:24 +02:00
tests fix uninitialized wave_color due to regression after rainbow wave color enablement in double dc sweeps; more bus_tap.sym usage in examples; make bus_tap.sym work correctly for all netlist formats 2023-05-27 23:36:10 +02:00
xschem_library fix some errors found by Joanne in test_bus_tap.sch 2023-05-31 00:14:22 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update copyright info to 2023 2023-05-21 12:52:19 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in get rid of stdint.h in postscript jpeg export code 2023-01-25 02:25:24 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions