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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers e4d9594065 small cosmetic changes in hash tables (initialization of next pointer) 2024-10-14 12:13:19 +02:00
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scconfig fix escape recognition in translate3(), so in symbol texts it is possible to write \\@name to an instance attribute to get literal @name in displayed text instead of the instance name. fix typo in tutorial_use_existing_subckt.html. some schematic updates (no more enable show_pin_net_names tcl variable) 2024-08-28 09:39:43 +02:00
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xschem_library added mux21.sch and mux21.sym in logic/, testcase in testbench.sch 2024-10-13 02:07:36 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions