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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers e01f545567 --diff option to visually compare two different (versions of) schematics 2022-12-13 13:51:33 +01:00
XSchemWin test and get reading schematics from the web on Windows working 2022-11-18 16:06:06 +01:00
doc --diff option to visually compare two different (versions of) schematics 2022-12-13 13:51:33 +01:00
scconfig fixed xcb detection (but disabled for now) 2022-12-08 14:19:02 +01:00
src --diff option to visually compare two different (versions of) schematics 2022-12-13 13:51:33 +01:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library added commented lines for antialiasing; JL:cairo_set_line_width should only be called with has_x as xctx->cairo_ctx and xctx->cairo_save_ctx is NULL when run with -x; JL:XCopyArea must be called to draw correctly with Cairo on Windows 2022-12-02 16:43:01 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in better recognize unknown commands in scheduler.c, re-enabed XCB detection in scconfig (although not used). 2022-12-07 11:32:40 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions