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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik dddaae5099 removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits. 2021-01-12 00:47:56 +01:00
XSchemWin delete(): clear lab_show.sym symbols if nets get unhilight after wire deletion 2021-01-08 05:26:37 +01:00
doc fix uncommented line (xschem start window) in xschemrc and link in doc main html page 2021-01-05 03:53:55 +01:00
scconfig add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports 2021-01-06 00:12:04 +01:00
src removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits. 2021-01-12 00:47:56 +01:00
tests redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
xschem_library removed redundant update_conn_cues() in some graphic operations; lower priority mux operator for logic sim, Dont change logic value added ("U"), ability to simulate bidirectional switches and simple logic MOS transistor networks. added sample circuits. 2021-01-12 00:47:56 +01:00
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Changelog fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli 2020-12-17 03:48:34 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions