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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik d7b0c27775 hiertEDAx: don\t split on escaped white space. test schematic with weird instance/net names 2020-11-24 15:25:37 +01:00
XSchemWin updated Changelog 2020-11-20 19:26:13 +01:00
doc "Delete files" menu command added 2020-10-24 23:46:19 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src hiertEDAx: don\t split on escaped white space. test schematic with weird instance/net names 2020-11-24 15:25:37 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library hiertEDAx: don\t split on escaped white space. test schematic with weird instance/net names 2020-11-24 15:25:37 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions