47 lines
1.6 KiB
Plaintext
47 lines
1.6 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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function0="1 ~"
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format="@name @pinlist @symname WN=@WN WP=@WP LLN=@LLN LLP=@LLP m=@m"
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verilog_primitive=true
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verilog_format="assign #80 @@Z = ~ @@A ;"
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template="name=X1 WN=15u WP=45u LLN=3u LLP=3u m=1"
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}
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V {}
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S {}
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E {}
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L 4 -40 0 -27.5 0 {}
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L 4 -27.5 -20 -27.5 20 {}
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L 4 -27.5 -20 16.25 0 {}
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L 4 -27.5 20 16.25 0 {}
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L 4 26.25 0 40 0 {}
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B 5 37.5 -2.5 42.5 2.5 {name=Z dir=out }
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B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in goto=0 propag=0}
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A 4 21.25 -0 5 180 360 {}
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T {@name} -26.25 -5 0 0 0.2 0.2 {}
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T {@symname} -26.25 35 0 0 0.2 0.2 {}
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T {@WP\\/@LLP\\/@m} -16.25 -25 0 0 0.2 0.2 {}
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T {@WN\\/@LLN\\/@m} -16.25 15 0 0 0.2 0.2 {}
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T {@#Z:net_name} 25 7.5 0 0 0.15 0.15 {layer=15}
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T {@#A:net_name} -35 7.5 0 1 0.15 0.15 {layer=15}
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