stefan schippers
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20359ed43e
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update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions
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2024-11-12 20:23:18 +01:00 |
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stefan schippers
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9c750b5044
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add @#pin:spice_get_voltage attribute for pin texts that displays voltage of net attached to pin. remove net_name=... attributes from symbols and instance global attributes since it is no more used. set default value for show_pin_net_names to 1.
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2024-05-02 10:32:12 +02:00 |
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stefan schippers
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94bccc08d9
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do not duplicate empty strings as NULLs in hash tables
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2023-10-09 12:49:11 +02:00 |
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Stefan Frederik
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629917cfcd
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new find_inst_to_be_redrawn() implementation to recalculate area to be redrawn with/without show net names on symbol pins, simplified new_window() call in callback `x` command, code formatting in globals.c, added xschem get [xy]origin commands
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2021-12-03 19:15:07 +01:00 |
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Stefan Frederik
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cc993bfe44
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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Stefan Schippers
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59d4608ac0
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completely eliminated match_symbol() (which in turn may call load_sym_def() ) calls from within load_sym_def(), even for aligning LCC schematic pin ordering to symbol. A dedicated "align_sch_pins_with_sym()" together with "get_sym_type()" does the job in O(N) instead of using a sort routine.
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2020-09-27 12:41:36 +02:00 |
schippes
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8dac4753f7
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Verilog and vhdl netlisters: print as instance parameters all params listed in instance properties, excluding "name" and all params not listed in template
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2020-08-10 14:15:36 +02:00 |
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Stefan SChippers
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5e8df730a0
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |