v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=subcircuit
function0="1 ~"
format="@name @pinlist @symname WN=@WN WP=@WP LLN=@LLN LLP=@LLP m=@m"
verilog_primitive=true
verilog_format="assign #80 @@Z = ~ @@A ;"
template="name=X1 WN=15u WP=45u LLN=3u LLP=3u m=1"
}
V {}
S {}
E {}
L 4 -40 0 -27.5 0 {}
L 4 -27.5 -20 -27.5 20 {}
L 4 -27.5 -20 16.25 0 {}
L 4 -27.5 20 16.25 0 {}
L 4 26.25 0 40 0 {}
B 5 37.5 -2.5 42.5 2.5 {name=Z dir=out }
B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in  goto=0 propag=0}
A 4 21.25 -0 5 180 360 {}
T {@name} -26.25 -5 0 0 0.2 0.2 {}
T {@symname} -26.25 35 0 0 0.2 0.2 {}
T {@WP\\/@LLP\\/@m} -16.25 -25 0 0 0.2 0.2 {}
T {@WN\\/@LLN\\/@m} -16.25 15 0 0 0.2 0.2 {}
T {@#Z:net_name} 25 7.5 0 0 0.15 0.15 {layer=15}
T {@#A:net_name} -35 7.5 0 1 0.15 0.15 {layer=15}