2024-11-05 20:09:04 +01:00
2024-10-31 16:50:59 +01:00

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions

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Description
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Readme GPL-2.0
62 MiB
Languages
C 72.7%
Tcl 16.3%
Awk 8.2%
Yacc 0.8%
Scheme 0.5%
Other 1.4%