A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Go to file
Stefan Frederik b6b6bb4f27 Fix: add symbol to space-hash in place_symbol() must be done before invoking symbol_bbox(); optimized eval_logic_expr() 2021-01-01 01:10:43 +01:00
XSchemWin added new examples to windows install [Joanne] 2020-12-30 12:16:34 +01:00
doc redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
scconfig -a -m check for unbound instances (Joanne fix) 2020-12-23 15:57:28 +01:00
src Fix: add symbol to space-hash in place_symbol() must be done before invoking symbol_bbox(); optimized eval_logic_expr() 2021-01-01 01:10:43 +01:00
tests redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
xschem_library Fix: add symbol to space-hash in place_symbol() must be done before invoking symbol_bbox(); optimized eval_logic_expr() 2021-01-01 01:10:43 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS populating xschem git repo 2020-08-08 15:47:34 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli 2020-12-17 03:48:34 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md Update README_MacOS.md 2020-12-12 02:18:39 +01:00
config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions