A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Go to file

stefan schippers b30eda3bb0 remove unused file		2023-04-28 17:58:35 +02:00
XSchemWin	Correct menu accelerator shown for "merge" function (b key)	2023-04-11 09:33:25 +02:00
doc	doc updates (sch/sym generators, aka pcells)	2023-04-28 12:03:56 +02:00
scconfig	change preprocessor defined(HAS_CAIRO) to HAS_CAIRO==1	2023-04-09 15:36:06 +02:00
src	remove unused file	2023-04-28 17:58:35 +02:00
tests	Doc updates (sim_pinnumber), example circuits update	2022-10-17 12:45:48 +02:00
xschem_library	remove unused file	2023-04-28 17:58:35 +02:00
.gitignore	gitignore update	2023-01-16 13:41:16 -07:00
AUTHORS	…
CMakeLists.txt	Added png and embedded graphs to ps and pdf export	2023-01-15 21:34:43 -07:00
Changelog	Update Changelog	2022-07-28 10:31:07 +02:00
INSTALL	…
LICENSE	…
Makefile	…
Makefile.conf.in	added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present	2023-01-18 03:33:28 +01:00
README	…
README.md	…
README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
config.h.in	get rid of stdint.h in postscript jpeg export code	2023-01-25 02:25:24 +01:00
configure	…

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions