luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,847 Commits 3 Branches 10 Tags 91 MiB
C 71.3%
Tcl 16%
Awk 8.1%
Roff 2%
Yacc 0.7%
Other 1.8%
Go to file
stefan schippers b23d7518bb find_inst_to_be_redrawn(): add `lvs_ignore=short` devices to list, fix uninitialized xctx->inst_redraw_table 2023-06-06 18:40:27 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin fix some errors found by Joanne in test_bus_tap.sch 2023-05-31 00:14:22 +02:00
doc documentation updates 2023-06-05 11:53:51 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src find_inst_to_be_redrawn(): add `lvs_ignore=short` devices to list, fix uninitialized xctx->inst_redraw_table 2023-06-06 18:40:27 +02:00
tests function reset_flags() set flags on symbols and instances; call reset_flags before rebuilding connectivity to update cached values; add short.sym component that can be used to short two nets together (and remove the short using *_ignore=true); instcheck(): do not proces instances that have *_ignore=true set. 2023-06-06 08:42:43 +02:00
xschem_library added global tcl variable `lvs_ignore` that can be used to enable instance or symbol attributes `lvs_ignore=open` or `lvs_ignore=short` while netlisting, added `test_lvs_ignore.sch` example 2023-06-06 15:22:45 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update copyright info to 2023 2023-05-21 12:52:19 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in get rid of stdint.h in postscript jpeg export code 2023-01-25 02:25:24 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions