A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Go to file
Stefan Frederik b1a1442012 allow spaces in bussed nodes (A B,CC,D\ C, A B[3:0]), dont dump double quoted net names in netlists 2020-11-29 00:00:55 +01:00
XSchemWin added some comments 2020-11-26 04:01:11 +01:00
doc "Delete files" menu command added 2020-10-24 23:46:19 +02:00
scconfig added some comments 2020-11-26 04:01:11 +01:00
src allow spaces in bussed nodes (A B,CC,D\ C, A B[3:0]), dont dump double quoted net names in netlists 2020-11-29 00:00:55 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library fix repeated character in RE, fix changed syntax in verilog example 2020-11-28 20:08:40 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS populating xschem git repo 2020-08-08 15:47:34 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog updated Changelog 2020-11-20 19:26:13 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions