A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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stefan schippers aadb87d255 update xschemtest.tcl netlist hashes		2026-01-23 13:49:48 +01:00
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doc	fix arbitrary widths in shapes, add "xschem get change_lw", "xschem get min_lw", "xschem set change_lw", cached tcl var "change_lw" into xctx->change_lw	2025-12-01 10:11:19 +01:00
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src	spice netlist: when m=1 (device/subckt multiplicity) dont set it in device netlist lines (redundant and in some cases not accepted)	2026-01-23 13:12:41 +01:00
tests	update xschemtest.tcl netlist hashes	2026-01-23 13:49:48 +01:00
xschem_library	gnd.sym: set default label to 0 instead of GND (better compatibility with simulators)	2026-01-22 10:11:43 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions