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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers a8e95e220b if a custom format netlist is given (for example lvs_netlist) and lvs_netlist attribute in instance or symbol is existing but empty device will not be netlisted 2023-03-10 18:36:55 +01:00
XSchemWin Make joanne fix for SPICE_DATA preprocessor macro comparison apply for unix as well 2023-02-27 22:32:28 +01:00
doc instance attribute "hide=true" will make the instance display as a bounding box only 2023-03-10 04:42:21 +01:00
scconfig set fatal flag in require() for type checks 2023-01-25 11:45:33 +01:00
src if a custom format netlist is given (for example lvs_netlist) and lvs_netlist attribute in instance or symbol is existing but empty device will not be netlisted 2023-03-10 18:36:55 +01:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library update test_ngspice.sch example circuit 2023-03-09 20:44:51 +01:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions