194 lines
5.2 KiB
XML
194 lines
5.2 KiB
XML
v {xschem version=3.4.7RC file_version=1.2}
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G {}
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K {}
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V {}
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S {}
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E {}
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B 2 80 -880 1140 -510 {flags=graph
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y1=0
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y2=3.3
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ypos1=0.27131944
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ypos2=4.2824898
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divy=5
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subdivy=1
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unity=1
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x1=2.7777218e-05
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x2=9.3313218e-05
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divx=5
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subdivx=1
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xlabmag=1.0
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ylabmag=1.0
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node="d[5..0];d5,d4,d3,d2,d1,d0
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valid_a
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clk
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start
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d0
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d1
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d2
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d3
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d4
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d5
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xtest.sample
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xtest.comp_a"
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color="8 4 4 8 10 10 10 10 10 10 4 20"
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dataset=-1
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unitx=1
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logx=0
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logy=0
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digital=1
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linewidth_mult=1}
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B 2 80 -1640 1140 -920 {flags=graph
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y1=-0.35
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y2=4.9
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=2.7777218e-05
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x2=9.3313218e-05
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divx=5
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subdivx=1
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xlabmag=1.0
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ylabmag=1.0
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dataset=-1
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unitx=1
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logx=0
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logy=0
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digital=0
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color="4 8 10 9"
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node="INPUT
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xtest.test_v
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i(vamm)
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xtest.sample 0.05 *"
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linewidth_mult=1
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hcursor1_y=1.0550322}
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T { A simple DAC so that the result may be compared to the input.} 800 -250 0 0 0.4 0.4 {}
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T {Analog conversion for plotting} 220 -140 0 0 0.4 0.4 {}
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T {This is an example of a true mixed mode
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(analog + Digital) simulation using ngspice
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for the analog part and Icarus Verilog
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(or Verilator) for the verilog part.
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Instructions
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- You need Verilator and / or Icarus verilog installed.
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- Icarus verilog must be built with the --enable-libvvp option.
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- Build the icarus / Verilator object
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(use the provided launchers)
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- Edit the sar_adc/sar_adc_vlog.sym attributes.
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There are two device_model attributes. Put an asterisc
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before the device_model attribute you want *NOT* to use.
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Example below enables Verilator object:
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***Icarus_verilog***
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*device_model=".model dut d_cosim simulation=\\"ivlng\\" sim_args=[\\"adc\\"]"
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***Verilator***
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device_model=".model dut d_cosim simulation=\\"./adc.so\\""
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} 1150 -1470 0 0 0.7 0.7 {}
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N 160 -290 160 -270 {lab=CLK}
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N 1330 -120 1330 -100 {lab=SUM}
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N 280 -290 280 -270 {lab=START}
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N 540 -290 540 -270 {lab=INPUT}
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N 50 -290 50 -270 {lab=VCC}
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N 840 -120 1330 -120 {lab=SUM}
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N 840 -210 840 -180 {lab=D5}
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N 920 -210 920 -180 {lab=D4}
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N 1000 -210 1000 -180 {lab=D3}
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N 1080 -210 1080 -180 {lab=D2}
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N 1160 -210 1160 -180 {lab=D1}
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N 1240 -210 1240 -180 {lab=D0}
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N 40 -140 40 -120 {lab=CLK}
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C {vsource.sym} 160 -240 0 0 {name=ACLOCK value=""
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format="@name @@m @@p clock"
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device_model=".model clock d_osc cntl_array=[-1 1] freq_array=[1Meg 1Meg]"
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spice_ignore=true}
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C {lab_pin.sym} 160 -210 0 0 {name=p25 lab=0}
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C {lab_pin.sym} 160 -290 0 0 {name=p34 lab=CLK}
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C {ammeter.sym} 1330 -70 0 0 {name=VAMM savecurrent=0 spice_ignore=0}
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C {lab_pin.sym} 1330 -40 0 0 {name=p35 lab=0}
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C {vsource.sym} 280 -240 0 0 {name=VPULSE value="PULSE 0 \{vcc\} 0.2u 10n 10n 1.3u 10u" savecurrent=false}
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C {lab_pin.sym} 280 -210 0 0 {name=p37 lab=0}
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C {lab_pin.sym} 280 -290 0 0 {name=p38 lab=START}
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C {vsource.sym} 540 -240 0 0 {name=VTEST value="PULSE 0 3 0 200u 200u 1u 401u" savecurrent=false}
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C {lab_pin.sym} 540 -210 0 0 {name=p39 lab=0}
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C {lab_pin.sym} 540 -290 0 0 {name=p40 lab=INPUT}
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C {code_shown.sym} 700 -440 0 0 {name=COMMANDS only_toplevel=false value="
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.param VCC=3.3
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.control
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save all
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tran 10n 250u
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remzerovec
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write tb_sar_adc.raw
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.endc
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"}
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C {vsource.sym} 50 -240 0 0 {name=VVCC value='VCC' savecurrent=false}
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C {lab_pin.sym} 50 -210 0 0 {name=p1 lab=0}
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C {lab_pin.sym} 50 -290 0 0 {name=p41 lab=VCC}
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C {res.sym} 840 -150 0 0 {name=R2
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value=2
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 840 -210 0 0 {name=p42 lab=D5}
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C {res.sym} 920 -150 0 0 {name=R3
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value=4
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 920 -210 0 0 {name=p43 lab=D4}
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C {res.sym} 1000 -150 0 0 {name=R4
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value=8
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 1000 -210 0 0 {name=p44 lab=D3}
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C {res.sym} 1080 -150 0 0 {name=R5
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value=16
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 1080 -210 0 0 {name=p45 lab=D2}
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C {res.sym} 1160 -150 0 0 {name=R6
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value=32
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 1160 -210 0 0 {name=p46 lab=D1}
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C {res.sym} 1240 -150 0 0 {name=R7
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value=64
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 1240 -210 0 0 {name=p47 lab=D0}
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C {lab_pin.sym} 1330 -120 0 1 {name=p48 lab=SUM}
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C {sar_adc.sym} 450 -380 0 0 {name=xtest}
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C {lab_pin.sym} 300 -410 0 0 {name=p7 lab=INPUT}
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C {lab_pin.sym} 300 -390 0 0 {name=p8 lab=VCC}
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C {lab_pin.sym} 300 -370 0 0 {name=p9 lab=START}
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C {lab_pin.sym} 600 -410 0 1 {name=p10 lab=VALID}
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C {lab_pin.sym} 600 -390 0 1 {name=p11 lab=D[5..0]}
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C {lab_pin.sym} 300 -350 0 0 {name=p12 lab=CLK}
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C {launcher.sym} 150 -490 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/tb_sar_adc.raw tran"
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}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {dac_bridge.sym} 330 -160 0 0 {name=A2 dac_bridge_model= dac_buff
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device_model=".model dac_buff dac_bridge input_load=1e-15 t_rise=10n t_fall=10n
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+ out_low=0 out_high=3.3"
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}
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C {lab_pin.sym} 300 -160 0 0 {name=p4 lab=VALID}
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C {lab_pin.sym} 360 -160 0 1 {name=p5 lab=VALID_A}
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C {vsource.sym} 40 -90 0 0 {name=VCLOCK value="pulse 0 'VCC' 500n 10n 10n 490n 1u"}
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C {lab_pin.sym} 40 -60 0 0 {name=p6 lab=0}
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C {lab_pin.sym} 40 -140 0 0 {name=p13 lab=CLK}
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C {launcher.sym} 1410 -390 0 0 {name=h1
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descr="Build Icarus Verilog object"
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tclcommand="execute 1 sh -c \\"cd $netlist_dir; iverilog -o adc [abs_sym_path adc.v]\\""
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}
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C {launcher.sym} 1410 -340 0 0 {name=h2
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descr="Build Verilator object"
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tclcommand="execute 1 sh -c \\"cd $netlist_dir; ngspice vlnggen [abs_sym_path adc.v]\\""
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}
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