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add ngspice_verilog_cosim examples

This commit is contained in:
stefan schippers 2025-04-11 18:37:55 +02:00
parent 232384f8fb
commit 34c2927f4f
15 changed files with 548 additions and 9 deletions
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5
scconfig/hooks.c
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@ -169,6 +169,11 @@ int hook_postarg()
append("/local/xschem/xschem-lib-path", "/");
append("/local/xschem/xschem-lib-path", "share/doc/xschem/ngspice");
append("/local/xschem/xschem-lib-path", ":");
append("/local/xschem/xschem-lib-path", get("/local/xschem/prefix"));
append("/local/xschem/xschem-lib-path", "/");
append("/local/xschem/xschem-lib-path", "share/doc/xschem/ngspice_verilog_cosim");
append("/local/xschem/xschem-lib-path", ":");
append("/local/xschem/xschem-lib-path", get("/local/xschem/prefix"));
append("/local/xschem/xschem-lib-path", "/");

21
src/xinit.c
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@ -2410,6 +2410,10 @@ int Tcl_AppInit(Tcl_Interp *inter)
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/ngspice",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/ngspice_verilog_cosim",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/logic",
tclgetvar("XSCHEM_SHAREDIR"));
@ -2442,19 +2446,20 @@ int Tcl_AppInit(Tcl_Interp *inter)
tclsetintvar("running_in_src_dir", running_in_src_dir);
#else /* windows */
char *up_hier=NULL, *win_xschem_library_path=NULL;
#define WIN_XSCHEM_LIBRARY_PATH_NUM 11
#define WIN_XSCHEM_LIBRARY_PATH_NUM 12
const char *WIN_XSCHEM_LIBRARY_PATH[WIN_XSCHEM_LIBRARY_PATH_NUM] = {
/*1*/ "xschem_library",
/*2*/ "xschem_library/devices",
/*3*/ "examples", /* See i==2 with WIN_XSCHEM_LIBRARY_PATH_NUM below */
/*4*/ "ngspice",
/*5*/ "logic",
/*6*/ "xschem_simulator",
/*7*/ "generators",
/*8*/ "inst_sch_select",
/*9*/ "binto7seg",
/*10*/ "pcb",
/*11*/ "rom8k" };
/*5*/ "ngspice_verilog_cosim",
/*6*/ "logic",
/*7*/ "xschem_simulator",
/*8*/ "generators",
/*9*/ "inst_sch_select",
/*10*/ "binto7seg",
/*11*/ "pcb",
/*12*/ "rom8k" };
GetModuleFileNameA(NULL, install_dir, MAX_PATH);
change_to_unix_fn(install_dir);
size_t dir_len=strlen(install_dir);

4
src/xschemrc
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@ -19,6 +19,7 @@
#### <install_root>/share/xschem/xschem_library/devices
#### <install_root>/share/doc/xschem/examples
#### <install_root>/share/doc/xschem/ngspice
#### <install_root>/share/doc/xschem/ngspice_verilog_cosim
#### <install_root>/share/doc/xschem/logic
#### <install_root>/share/doc/xschem/xschem_simulator
#### <install_root>/share/doc/xschem/generators
@ -33,6 +34,7 @@
#### ../xschem_library/devices
#### ../xschem_library/examples
#### ../xschem_library/ngspice
#### ../xschem_library/ngspice_verilog_cosim
#### ../xschem_library/logic
#### ../xschem_library/xschem_simulator
#### ../xschem_library/generators
@ -48,6 +50,7 @@
# append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library/devices
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/examples
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/ngspice
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/ngspice_verilog_cosim
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/logic
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/xschem_simulator
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/generators
@ -67,6 +70,7 @@
# append XSCHEM_LIBRARY_PATH ";${XSCHEM_SHAREDIR}/xschem_library/devices"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/examples"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/ngspice"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/ngspice_verilog_cosim"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/logic"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/xschem_simulator"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/generators"

6
xschem_library/Makefile
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@ -8,7 +8,7 @@ install: FORCE
$(SCCBOX) mkdir -p "$(system_library_dir)" "$(XDOCDIR)"/examples "$(XDOCDIR)"/pcb
$(SCCBOX) mkdir -p "$(XDOCDIR)"/logic "$(XDOCDIR)"/xTAG "$(XDOCDIR)"/binto7seg
$(SCCBOX) mkdir -p "$(XDOCDIR)"/symgen "$(XDOCDIR)"/ngspice "$(XDOCDIR)"/rulz-r8c33
$(SCCBOX) mkdir -p "$(XDOCDIR)"/generators
$(SCCBOX) mkdir -p "$(XDOCDIR)"/generators "$(XDOCDIR)"/ngspice_verilog_cosim
$(SCCBOX) mkdir -p "$(XDOCDIR)"/inst_sch_select
$(SCCBOX) mkdir -p "$(XDOCDIR)"/rom8k "$(XDOCDIR)"/gschem_import/sym
$(SCCBOX) install -f -d devices/*.sym "$(system_library_dir)"
@ -23,6 +23,9 @@ install: FORCE
$(SCCBOX) install -f -d inst_sch_select/*.* "$(XDOCDIR)"/inst_sch_select
$(SCCBOX) install -f -d xTAG/*.sym* "$(XDOCDIR)"/xTAG
$(SCCBOX) install -f -d xTAG/*.sch "$(XDOCDIR)"/xTAG
$(SCCBOX) install -f -d ngspice_verilog_cosim/*.sym "$(XDOCDIR)"/ngspice_verilog_cosim
$(SCCBOX) install -f -d ngspice_verilog_cosim/*.sch "$(XDOCDIR)"/ngspice_verilog_cosim
$(SCCBOX) install -f -d ngspice_verilog_cosim/*.v "$(XDOCDIR)"/ngspice_verilog_cosim
$(SCCBOX) install -f -d logic/*.sym "$(XDOCDIR)"/logic
$(SCCBOX) install -f -d logic/*.sch "$(XDOCDIR)"/logic
$(SCCBOX) install -f -d logic/stimuli.* "$(XDOCDIR)"/logic
@ -48,6 +51,7 @@ uninstall: FORCE
"$(system_library_dir)" \
"$(XDOCDIR)"/examples/* "$(XDOCDIR)"/pcb/* \
"$(XDOCDIR)"/ngspice/* "$(XDOCDIR)"/symgen/* "$(XDOCDIR)"/logic/* "$(XDOCDIR)"/xTAG/* \
"$(XDOCDIR)"/ngspice_verilog_cosim/* \
"$(XDOCDIR)"/rom8k/* "$(XDOCDIR)"/xschem_simulator/* "$(XDOCDIR)"/binto7seg/* \
"$(XDOCDIR)"/rulz-r8c33/* "$(XDOCDIR)"/generators/* "$(XDOCDIR)"/inst_sch_select/* \
"$(XDOCDIR)"/gschem_import/*.sym \

45
xschem_library/ngspice_verilog_cosim/adc.v Normal file
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@ -0,0 +1,45 @@
// Digital control for a successive approximation ADC with switched capacitors.
`timescale 100ns/100ns
module adc(Clk, Comp, Start, Sample, Done, Result);
parameter Bits=6;
input wire Clk, Comp, Start;
output reg Sample, Done;
output reg [Bits - 1 : 0] Result;
reg [Bits - 1 : 0] SR;
reg Running;
initial begin
$display("ADC simulation starting");
Done = 0;
Sample = 0;
Result = 0;
Running = 0;
end
always @(posedge(Clk)) begin
if (Running) begin
if (Sample) begin
Sample <= 0;
SR[Bits - 1] <= 1;
Result[Bits - 1] <= 1;
end else if (SR != 0) begin
Result <= (Comp ? (Result & ~SR) : Result) | (SR >> 1);
SR <= SR >> 1;
if (SR == 1) begin
Running <= 0;
Done <= 1;
end
end
end else if (Start) begin
Running <= 1;
Sample <= 1;
Done <= 0;
SR <= 0;
Result <= 0;
end
end
endmodule

27
xschem_library/ngspice_verilog_cosim/ainv.sch Normal file
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@ -0,0 +1,27 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 170 -210 170 -150 {lab=OUT}
N 170 -310 170 -240 {lab=VDD}
N 170 -120 170 -50 {lab=0}
N 130 -240 130 -120 {lab=IN}
N 170 -180 240 -180 {lab=OUT}
N 70 -180 130 -180 {lab=IN}
C {nmos4.sym} 150 -120 0 0 {name=MN model=N1
format="@name @pinlist @model"
device_model=".model n1 nmos
+ level=2 vto=0.5 kp=24e-6 gamma=0.15 phi=0.65 lambda=0.015 xj=0.5e-6
"}
C {pmos4.sym} 150 -240 0 0 {name=MP model=P1
format="@name @pinlist @model"
device_model=".model p1 pmos
+ level=2 vto=-0.5 kp=8.5e-6 gamma=0.4 phi=0.65 lambda=0.05 xj=0.5e-6
"}
C {ipin.sym} 70 -180 0 0 {name=p1 lab=IN}
C {opin.sym} 240 -180 0 0 {name=p2 lab=OUT}
C {lab_pin.sym} 170 -50 0 0 {name=p3 sig_type=std_logic lab=0}
C {ipin.sym} 170 -310 0 0 {name=p4 lab=VDD}

22
xschem_library/ngspice_verilog_cosim/ainv.sym Normal file
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@ -0,0 +1,22 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 50 0 60 0 {}
L 4 -60 0 -40 0 {}
L 4 0 -70 0 -20 {}
B 5 -62.5 -2.5 -57.5 2.5 {name=IN dir=in}
B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out}
B 5 -2.5 -72.5 2.5 -67.5 {name=VDD dir=in}
A 4 45 0 5 180 360 {}
P 4 4 -40 40 -40 -40 40 0 -40 40 {}
T {@symname} -36 39 0 0 0.3 0.3 {}
T {@name} 5 -32 0 0 0.3 0.3 {}
T {VDD} 5 -64 0 0 0.2 0.2 {}
T {OUT} 20 -4 0 1 0.2 0.2 {}
T {IN} -35 -4 0 0 0.2 0.2 {}

22
xschem_library/ngspice_verilog_cosim/ccap.sch Normal file
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@ -0,0 +1,22 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 340 -240 340 -160 {lab=TAIL}
N 340 -320 340 -300 {lab=IN}
N 300 -160 370 -160 {lab=TAIL}
N 80 -320 340 -320 {lab=IN}
N 80 -160 180 -160 {lab=CTL}
N 80 -230 240 -230 {lab=VCC}
C {ipin.sym} 80 -320 0 0 {name=p1 lab=IN}
C {ipin.sym} 80 -230 0 0 {name=p2 lab=VCC}
C {ipin.sym} 80 -160 0 0 {name=p3 lab=CTL}
C {ainv.sym} 240 -160 0 0 {name=XINV}
C {lab_pin.sym} 370 -160 0 1 {name=p5 lab=TAIL}
C {capa.sym} 340 -270 0 0 {name=CB
m=1
value=c='C'
footprint=1206
device="ceramic capacitor"}

22
xschem_library/ngspice_verilog_cosim/ccap.sym Normal file
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@ -0,0 +1,22 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname C=@C"
template="name=x1 C=1p"
}
V {}
S {}
E {}
L 4 -60 -20 -40 -20 {}
L 4 -60 0 -40 0 {}
L 4 -60 20 -40 20 {}
B 5 -62.5 -22.5 -57.5 -17.5 {name=IN dir=in}
B 5 -62.5 -2.5 -57.5 2.5 {name=VCC dir=in}
B 5 -62.5 17.5 -57.5 22.5 {name=CTL dir=in}
P 4 5 40 -30 -40 -30 -40 30 40 30 40 -30 {}
T {@symname} 36 -6 0 1 0.2 0.2 {}
T {@name} -35 -52 0 0 0.3 0.3 {}
T {IN} -35 -24 0 0 0.2 0.2 {}
T {VCC} -35 -4 0 0 0.2 0.2 {}
T {CTL} -35 16 0 0 0.2 0.2 {}
T {C=@C} -35 38 0 0 0.3 0.3 {}

101
xschem_library/ngspice_verilog_cosim/sar_adc.sch Normal file
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@ -0,0 +1,101 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {}
V {}
S {}
E {}
P 4 7 990 -530 990 -490 995 -490 990 -480 985 -490 990 -490 990 -530 {fill=full}
T {Analog conversion for plotting} 750 -110 0 0 0.4 0.4 {}
T {Change device_model attribute
to simulate this verilog block
with Icarus Verilog or Verilator} 770 -605 0 0 0.4 0.4 {layer=4}
N 560 -60 560 -40 {lab=0}
N 860 -180 890 -180 {lab="%vd(TEST_V VREF)"}
N 950 -180 980 -180 {lab=COMP}
N 180 -540 180 -480 {lab=IIN}
N 180 -420 180 -380 {lab=TEST_V}
N 180 -380 360 -380 {lab=TEST_V}
N 360 -120 560 -120 {lab=TEST_V}
N 360 -240 360 -120 {lab=TEST_V}
N 360 -840 500 -840 {lab=TEST_V}
N 360 -720 500 -720 {lab=TEST_V}
N 360 -600 500 -600 {lab=TEST_V}
N 360 -480 500 -480 {lab=TEST_V}
N 360 -360 500 -360 {lab=TEST_V}
N 360 -240 500 -240 {lab=TEST_V}
N 360 -480 360 -380 {lab=TEST_V}
N 360 -840 360 -720 {lab=TEST_V}
N 360 -720 360 -600 {lab=TEST_V}
N 360 -600 360 -480 {lab=TEST_V}
N 360 -380 360 -360 {lab=TEST_V}
N 360 -360 360 -240 {lab=TEST_V}
C {ipin.sym} 80 -180 0 0 {name=p1 lab=INPUT}
C {ipin.sym} 80 -160 0 0 {name=p2 lab=VREF}
C {ipin.sym} 80 -140 0 0 {name=p3 lab=START}
C {opin.sym} 170 -140 0 0 {name=p4 lab=VALID}
C {ipin.sym} 80 -100 0 0 {name=p5 lab=CLK}
C {opin.sym} 170 -120 0 0 {name=p6 lab=D[5..0]}
C {ccap.sym} 560 -820 0 0 {name=xb5 C=1p}
C {lab_pin.sym} 500 -820 0 0 {name=p8 lab=VREF}
C {lab_pin.sym} 500 -800 0 0 {name=p9 lab=D5}
C {ccap.sym} 560 -700 0 0 {name=xb4 C="'1p / 2'"}
C {lab_pin.sym} 500 -700 0 0 {name=p11 lab=VREF}
C {lab_pin.sym} 500 -680 0 0 {name=p12 lab=D4}
C {ccap.sym} 560 -580 0 0 {name=xb3 C="'1p / 4'"}
C {lab_pin.sym} 500 -580 0 0 {name=p14 lab=VREF}
C {lab_pin.sym} 500 -560 0 0 {name=p15 lab=D3}
C {ccap.sym} 560 -460 0 0 {name=xb2 C="'1p / 8'"}
C {lab_pin.sym} 500 -460 0 0 {name=p17 lab=VREF}
C {lab_pin.sym} 500 -440 0 0 {name=p18 lab=D2}
C {ccap.sym} 560 -340 0 0 {name=xb1 C="'1p / 16'"}
C {lab_pin.sym} 500 -340 0 0 {name=p20 lab=VREF}
C {lab_pin.sym} 500 -320 0 0 {name=p21 lab=D1}
C {ccap.sym} 560 -220 0 0 {name=xb0 C="'1p / 32'"}
C {lab_pin.sym} 500 -220 0 0 {name=p23 lab=VREF}
C {lab_pin.sym} 500 -200 0 0 {name=p24 lab=D0}
C {capa.sym} 560 -90 0 0 {name=CLAST
m=1
value="'1p / 32'"
footprint=1206
device="ceramic capacitor"}
C {lab_pin.sym} 560 -40 0 0 {name=p26 lab=0}
C {adc_bridge.sym} 920 -180 0 0 {name=ACOMP adc_bridge_model= comparator
device_model=".model comparator adc_bridge in_low=0 in_high=0"}
C {lab_pin.sym} 860 -180 0 0 {name=p27 lab="%vd(TEST_V VREF)"}
C {lab_pin.sym} 980 -180 0 1 {name=p28 lab=COMP}
C {tgate.sym} 120 -540 0 0 {name=XSAMPLE}
C {lab_pin.sym} 60 -540 0 0 {name=p29 lab=INPUT}
C {lab_pin.sym} 180 -540 0 1 {name=p30 lab=IIN}
C {lab_pin.sym} 60 -580 0 0 {name=p31 lab=SAMPLE}
C {lab_pin.sym} 60 -620 0 0 {name=p32 lab=VREF}
C {res.sym} 180 -450 0 0 {name=R1
value=1k
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 180 -400 0 1 {name=p33 lab=TEST_V}
C {sar_adc_vlog.sym} 930 -400 0 0 {name=ADUT model=dut
***Icarus_verilog***
device_model=".model dut d_cosim simulation=\\"ivlng\\" sim_args=[\\"adc\\"]"
***Verilator***
*device_model=".model dut d_cosim simulation=\\"./adc.so\\""
tclcommand="edit_file [abs_sym_path adc.v]"
}
C {lab_pin.sym} 770 -440 0 0 {name=p7 lab=CLK}
C {lab_pin.sym} 770 -400 0 0 {name=p10 lab=COMP}
C {lab_pin.sym} 1090 -400 0 1 {name=p13 lab=VALID}
C {lab_pin.sym} 1090 -360 0 1 {name=p16 lab=~D[5..0]}
C {lab_pin.sym} 1090 -440 0 1 {name=p19 lab=SAMPLE}
C {lab_pin.sym} 770 -360 0 0 {name=p22 lab=START}
C {dac_bridge.sym} 900 -70 0 0 {name=A1 dac_bridge_model= dac_buff
device_model=".model dac_buff dac_bridge input_load=1e-15 t_rise=10n t_fall=10n
+ out_low=0 out_high=3.3"}
C {lab_pin.sym} 870 -70 0 0 {name=p34 lab=COMP}
C {lab_pin.sym} 930 -70 0 1 {name=p35 lab=COMP_A}
C {noconn.sym} 170 -120 0 0 {name=l1}
C {noconn.sym} 950 -180 3 0 {name=l2}
C {noconn.sym} 860 -180 3 0 {name=l3}

26
xschem_library/ngspice_verilog_cosim/sar_adc.sym Normal file
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@ -0,0 +1,26 @@
v {xschem version=3.4.7RC file_version=1.2}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
T {@symname} -49.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -52 0 0 0.2 0.2 {}
P 4 5 130 -40 -130 -40 -130 40 130 40 130 -40 {}
B 5 -152.5 -32.5 -147.5 -27.5 {name=INPUT dir=in}
L 4 -150 -30 -130 -30 {}
T {INPUT} -125 -34 0 0 0.2 0.2 {}
B 5 -152.5 -12.5 -147.5 -7.5 {name=VREF dir=in}
L 4 -150 -10 -130 -10 {}
T {VREF} -125 -14 0 0 0.2 0.2 {}
B 5 -152.5 7.5 -147.5 12.5 {name=START dir=in}
L 4 -150 10 -130 10 {}
T {START} -125 6 0 0 0.2 0.2 {}
B 5 147.5 -32.5 152.5 -27.5 {name=VALID dir=out}
L 4 130 -30 150 -30 {}
T {VALID} 125 -34 0 1 0.2 0.2 {}
B 5 147.5 -12.5 152.5 -7.5 {name=D[5..0] dir=out}
L 4 130 -10 150 -10 {}
T {D[5..0]} 125 -14 0 1 0.2 0.2 {}
B 5 -152.5 27.5 -147.5 32.5 {name=CLK dir=in}
L 4 -150 30 -130 30 {}
T {CLK} -125 26 0 0 0.2 0.2 {}

35
xschem_library/ngspice_verilog_cosim/sar_adc_vlog.sym Normal file
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@ -0,0 +1,35 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {type=primitive
format="@name [ @@CLK @@COMP @@START ] [ @@SAMPLE @@VALID @@D[5..0] ] @model"
template="name=A1 model=sar_adc"}
V {}
S {}
E {}
L 4 -160 -40 -120 -40 {}
L 4 -160 0 -120 0 {}
L 4 120 0 160 0 {}
L 4 120 40 160 40 {}
L 4 120 -40 160 -40 {}
L 4 -160 40 -120 40 {}
B 5 -162.5 -42.5 -157.5 -37.5 {name=CLK
dir=in}
B 5 -162.5 -2.5 -157.5 2.5 {name=COMP
dir=in}
B 5 157.5 -2.5 162.5 2.5 {name=VALID
dir=out}
B 5 157.5 37.5 162.5 42.5 {name=D[5..0]
dir=out}
B 5 157.5 -42.5 162.5 -37.5 {name=SAMPLE
dir=out}
B 5 -162.5 37.5 -157.5 42.5 {name=START
dir=in}
P 4 5 -120 -80 120 -80 120 80 -120 80 -120 -80 {}
T {CLK} -110 -50 0 0 0.4 0.4 {}
T {COMP} -110 -10 0 0 0.4 0.4 {}
T {VALID} 110 -10 0 1 0.4 0.4 {}
T {D[5..0]} 110 30 0 1 0.4 0.4 {}
T {SAMPLE} 110 -50 0 1 0.4 0.4 {}
T {START} -110 30 0 0 0.4 0.4 {}
T {@symname} -120 -110 0 0 0.4 0.4 {}
T {@name} -120 90 0 0 0.4 0.4 {}

175
xschem_library/ngspice_verilog_cosim/tb_sar_adc.sch Normal file
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@ -0,0 +1,175 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 80 -880 1290 -510 {flags=graph
y1=0
y2=3.3
ypos1=0.27131944
ypos2=4.2824898
divy=5
subdivy=1
unity=1
x1=0
x2=0.00025
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node="d[5..0];d5,d4,d3,d2,d1,d0
valid_a
clk
start
d0
d1
d2
d3
d4
d5
xtest.sample
xtest.comp_a"
color="8 4 4 8 10 10 10 10 10 10 4 20"
dataset=-1
unitx=1
logx=0
logy=0
digital=1
linewidth_mult=1}
B 2 80 -1640 1290 -920 {flags=graph
y1=-0.35
y2=4.9
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.00025
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
digital=0
color="4 8 10"
node="INPUT
xtest.test_v
i(vamm)"
linewidth_mult=1}
T { A simple DAC so that the result may be compared to the input.} 800 -250 0 0 0.4 0.4 {}
T {Analog conversion for plotting} 220 -140 0 0 0.4 0.4 {}
N 160 -290 160 -270 {lab=CLK}
N 1330 -120 1330 -100 {lab=SUM}
N 280 -290 280 -270 {lab=START}
N 540 -290 540 -270 {lab=INPUT}
N 50 -290 50 -270 {lab=VCC}
N 840 -120 1330 -120 {lab=SUM}
N 840 -210 840 -180 {lab=D5}
N 920 -210 920 -180 {lab=D4}
N 1000 -210 1000 -180 {lab=D3}
N 1080 -210 1080 -180 {lab=D2}
N 1160 -210 1160 -180 {lab=D1}
N 1240 -210 1240 -180 {lab=D0}
N 40 -140 40 -120 {lab=CLK}
C {vsource.sym} 160 -240 0 0 {name=ACLOCK value=""
format="@name @@m @@p clock"
device_model=".model clock d_osc cntl_array=[-1 1] freq_array=[1Meg 1Meg]"
spice_ignore=true}
C {lab_pin.sym} 160 -210 0 0 {name=p25 lab=0}
C {lab_pin.sym} 160 -290 0 0 {name=p34 lab=CLK}
C {ammeter.sym} 1330 -70 0 0 {name=VAMM savecurrent=0 spice_ignore=0}
C {lab_pin.sym} 1330 -40 0 0 {name=p35 lab=0}
C {vsource.sym} 280 -240 0 0 {name=VPULSE value="PULSE 0 \{vcc\} 0.2u 10n 10n 1.3u 10u" savecurrent=false}
C {lab_pin.sym} 280 -210 0 0 {name=p37 lab=0}
C {lab_pin.sym} 280 -290 0 0 {name=p38 lab=START}
C {vsource.sym} 540 -240 0 0 {name=VTEST value="PULSE 0 3 0 200u 200u 1u 401u" savecurrent=false}
C {lab_pin.sym} 540 -210 0 0 {name=p39 lab=0}
C {lab_pin.sym} 540 -290 0 0 {name=p40 lab=INPUT}
C {code_shown.sym} 700 -440 0 0 {name=COMMANDS only_toplevel=false value="
.param VCC=3.3
.control
save all
tran 10n 250u
remzerovec
write tb_sar_adc.raw
.endc
"}
C {vsource.sym} 50 -240 0 0 {name=VVCC value='VCC' savecurrent=false}
C {lab_pin.sym} 50 -210 0 0 {name=p1 lab=0}
C {lab_pin.sym} 50 -290 0 0 {name=p41 lab=VCC}
C {res.sym} 840 -150 0 0 {name=R2
value=2
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 840 -210 0 0 {name=p42 lab=D5}
C {res.sym} 920 -150 0 0 {name=R3
value=4
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 920 -210 0 0 {name=p43 lab=D4}
C {res.sym} 1000 -150 0 0 {name=R4
value=8
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 1000 -210 0 0 {name=p44 lab=D3}
C {res.sym} 1080 -150 0 0 {name=R5
value=16
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 1080 -210 0 0 {name=p45 lab=D2}
C {res.sym} 1160 -150 0 0 {name=R6
value=32
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 1160 -210 0 0 {name=p46 lab=D1}
C {res.sym} 1240 -150 0 0 {name=R7
value=64
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 1240 -210 0 0 {name=p47 lab=D0}
C {lab_pin.sym} 1330 -120 0 1 {name=p48 lab=SUM}
C {sar_adc.sym} 450 -380 0 0 {name=xtest}
C {lab_pin.sym} 300 -410 0 0 {name=p7 lab=INPUT}
C {lab_pin.sym} 300 -390 0 0 {name=p8 lab=VCC}
C {lab_pin.sym} 300 -370 0 0 {name=p9 lab=START}
C {lab_pin.sym} 600 -410 0 1 {name=p10 lab=VALID}
C {lab_pin.sym} 600 -390 0 1 {name=p11 lab=D[5..0]}
C {lab_pin.sym} 300 -350 0 0 {name=p12 lab=CLK}
C {launcher.sym} 1030 -490 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/tb_sar_adc.raw tran"
}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {dac_bridge.sym} 330 -160 0 0 {name=A2 dac_bridge_model= dac_buff
device_model=".model dac_buff dac_bridge input_load=1e-15 t_rise=10n t_fall=10n
+ out_low=0 out_high=3.3"
}
C {lab_pin.sym} 300 -160 0 0 {name=p4 lab=VALID}
C {lab_pin.sym} 360 -160 0 1 {name=p5 lab=VALID_A}
C {vsource.sym} 40 -90 0 0 {name=VCLOCK value="pulse 0 'VCC' 500n 10n 10n 490n 1u"}
C {lab_pin.sym} 40 -60 0 0 {name=p6 lab=0}
C {lab_pin.sym} 40 -140 0 0 {name=p13 lab=CLK}
C {launcher.sym} 1030 -450 0 0 {name=h1
descr="Build Icarus Verilog object"
tclcommand="execute 1 sh -c \\"cd $netlist_dir; iverilog -o adc [abs_sym_path adc.v]\\""
}
C {launcher.sym} 1030 -410 0 0 {name=h2
descr="Build Verilator object"
tclcommand="execute 1 sh -c \\"cd $netlist_dir; ngspice vlnggen [abs_sym_path adc.v]\\""
}
C {launcher.sym} 1030 -360 0 0 {name=h3
descr="test"
tclcommand="execute 1 xclock"
}

19
xschem_library/ngspice_verilog_cosim/tgate.sch Normal file
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@ -0,0 +1,19 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 290 -240 290 -220 {lab=A}
N 290 -160 290 -140 {lab=B}
C {switch_ngspice.sym} 290 -190 0 0 {name=SWITCH model=TG
device_model=".MODEL TG SW( VT=1.5 RON=2k )"}
C {lab_pin.sym} 250 -190 0 0 {name=p1 lab=CTL}
C {lab_pin.sym} 290 -240 0 1 {name=p2 lab=A}
C {lab_pin.sym} 290 -140 0 1 {name=p3 lab=B}
C {lab_pin.sym} 250 -170 0 0 {name=p4 lab=0}
C {ipin.sym} 110 -170 0 0 { name=p5 lab=CTL }
C {iopin.sym} 110 -190 0 1 { name=p6 lab=B }
C {iopin.sym} 110 -210 0 1 { name=p7 lab=A }
C {ipin.sym} 110 -150 0 0 { name=p8 lab=VDD }
C {noconn.sym} 110 -150 0 1 {name=l1}

27
xschem_library/ngspice_verilog_cosim/tgate.sym Normal file
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@ -0,0 +1,27 @@
v {xschem version=3.4.7RC file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -10 0 10 -10 {}
L 4 10 -0 60 0 {}
L 4 -60 -40 -0 -40 {}
L 4 20 -80 20 -20 {dash=3}
L 4 -60 -80 20 -80 {dash=3}
L 4 -60 -0 -10 -0 {}
L 4 0 -40 -0 -20 {}
B 5 -62.5 -2.5 -57.5 2.5 {name=A dir=inout}
B 5 57.5 -2.5 62.5 2.5 {name=B dir=inout}
B 5 -62.5 -42.5 -57.5 -37.5 {name=CTL dir=in}
B 5 -62.5 -82.5 -57.5 -77.5 {name=VDD dir=in}
P 4 5 -40 -20 40 -20 40 20 -40 20 -40 -20 {}
T {@symname} 24.5 -76 0 0 0.3 0.3 {}
T {@name} 25 -52 0 0 0.3 0.3 {}
T {A} -55 6 0 0 0.2 0.2 {}
T {B} 55 6 0 1 0.2 0.2 {}
T {CTL} -55 -54 0 0 0.2 0.2 {}
T {VDD} -55 -94 0 0 0.2 0.2 {}