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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 93fe5bf414 fix handling empty return value of translate2() in load_sym_def() 2022-10-15 11:16:36 +02:00
XSchemWin update xschemtest, more robust spice flatten.awk netlist flattener, specifically when translating expressions containing electrical nodes and parameters, all these need to be translated/substituted. 2022-10-12 01:16:23 +02:00
doc doc updates (multi project setup, tutorial_xschem_libraries.html) 2022-10-14 11:23:46 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src fix handling empty return value of translate2() in load_sym_def() 2022-10-15 11:16:36 +02:00
tests my_fgets() 2022-10-13 13:43:01 +02:00
xschem_library wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names 2022-10-12 16:36:56 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions