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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 86bafe1f9b remove unconnected components in switch_level_sim.sch 2021-01-14 18:53:50 +01:00
XSchemWin delete(): clear lab_show.sym symbols if nets get unhilight after wire deletion 2021-01-08 05:26:37 +01:00
doc removed/updated obsolete keybinding descriptions, removed status check on Delete key events 2021-01-13 13:44:57 +01:00
scconfig uniquify __UNCONNECTED_NODE__ by appending a unique number to avoid shorting multiple missing connecting nodes 2021-01-14 18:12:02 +01:00
src uniquify __UNCONNECTED_NODE__ by appending a unique number to avoid shorting multiple missing connecting nodes 2021-01-14 18:12:02 +01:00
tests redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
xschem_library remove unconnected components in switch_level_sim.sch 2021-01-14 18:53:50 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions