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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 847d1df1b3 xschem logic_get: return X instead of empty string if net has never been assigned 2023-03-10 02:14:55 +01:00
XSchemWin Make joanne fix for SPICE_DATA preprocessor macro comparison apply for unix as well 2023-02-27 22:32:28 +01:00
doc add xschem logic_get command to get logic state of nets 2023-03-10 02:04:08 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions