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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 80ceb60749 doc: simulation html page updates 2021-11-21 00:09:25 +01:00
XSchemWin redundant code elimination in new_schematic(), fixed a memory leak in update_symbol() 2021-11-03 00:31:08 +01:00
doc doc: simulation html page updates 2021-11-21 00:09:25 +01:00
scconfig some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet 2021-11-16 22:28:10 +01:00
src add missing braces in update recent file submenu, fix file selector improperly setting main window title, added logic/test_mos_verilog.sch depletion mode verilog example 2021-11-20 23:44:19 +01:00
tests update license info 2021-07-27 16:42:54 +02:00
xschem_library depletion nmos transistor drawn with drain side low as this is the way it is used 2021-11-21 00:02:48 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions