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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 7e1f591b18 align TOK_TOKEN state change of translate() and translate2() to all other parsers 2023-05-02 18:54:27 +02:00
XSchemWin persistent load file dialog (Shift-Insert) now correctly handles generator script selection (do nothing until user adds () or (param1,param2,...) to generator name). 2023-04-29 00:28:24 +02:00
doc persistent load file dialog (Shift-Insert) now correctly handles generator script selection (do nothing until user adds () or (param1,param2,...) to generator name). 2023-04-29 00:28:24 +02:00
scconfig change preprocessor defined(HAS_CAIRO) to HAS_CAIRO==1 2023-04-09 15:36:06 +02:00
src align TOK_TOKEN state change of translate() and translate2() to all other parsers 2023-05-02 18:54:27 +02:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library updated test_mosgen.sch and mosgen examples 2023-05-02 18:39:14 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions