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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
2,863 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
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stefan schippers 7ace392d23 switch_ngspice.sym: add "device_model" attribute in template string, so a template model is given when placing the symbol 2024-10-03 18:34:40 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin proc ev, ev0, to_eng: evaluate expr at global scope so global vars will be expanded correctly ($path) 2024-05-29 09:41:52 +02:00
doc update developer_info.html (xschem print command description) 2024-09-30 17:22:31 +02:00
scconfig fix escape recognition in translate3(), so in symbol texts it is possible to write \\@name to an instance attribute to get literal @name in displayed text instead of the instance name. fix typo in tutorial_use_existing_subckt.html. some schematic updates (no more enable show_pin_net_names tcl variable) 2024-08-28 09:39:43 +02:00
src handle NULL analysis type in debug messages (extra_rawfile()), recursive value substitution in symbol displayed strings: if translated text begins with @ search for recursive upper level definitions for text following @, example: @model symbol text, instance has model=@modeln, upper instance has modeln=nfet: resolve symbol text and display "@model" as "nfet", proc inutile: add optional wait argument to block xschem while dialog displayed 2024-10-03 13:08:32 +02:00
tests update hash calculation in xschemtest.tcl for LCC_instances netlist (due to changes in schematic) 2024-09-10 22:38:44 +02:00
xschem_library switch_ngspice.sym: add "device_model" attribute in template string, so a template model is given when placing the symbol 2024-10-03 18:34:40 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog svg and ps/pdf export: do not include data for offscreen graphs or images to reduce file size 2024-09-24 11:10:30 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions