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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 77be19bc6a ind.sym artwork 2022-02-21 00:20:21 +01:00
XSchemWin add test_extracted_netlist circuit example 2022-02-18 15:11:44 +01:00
doc doc updates (graphs) 2022-02-15 01:28:29 +01:00
scconfig remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
src declared more functions static where possible and appropriate 2022-02-19 14:31:55 +01:00
tests fix wave panning if a non graph added, better error reporting in png writer function, better flags option names for special objejcts (image and graphs) 2022-01-21 02:18:07 +01:00
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config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions