A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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stefan schippers 76fe0d3ef3 tests/netlisting.tcl: better error checking. Distinguish a general failure from an ERC netlist error (xschem return code 10)		2024-05-17 00:48:47 +02:00
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tests	tests/netlisting.tcl: better error checking. Distinguish a general failure from an ERC netlist error (xschem return code 10)	2024-05-17 00:48:47 +02:00
xschem_library	if top level schematic has an associated symbol (.sym) file ensure their ports match, otherwise issue an error. if netlisting fails return non zero exit code if netlisting from command line	2024-05-09 02:10:45 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions