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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Schippers 7360982d7c removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
XSchemWin various graphic rendering fixes for the new "view instance pin net names" function. Fixed some errors in merge schematic in callback.c and paste.c 2020-10-02 03:21:22 +02:00
doc doc updates (developer info) 2020-10-09 03:04:49 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog fix Browse button in edit symbol prop dialog 2020-09-15 14:15:43 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions