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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 728cfb22fc print_spice_subckt_nodes(): remove closing bracket in case of tcleval(...) failure 2023-04-17 10:33:45 +02:00
XSchemWin Correct menu accelerator shown for "merge" function (b key) 2023-04-11 09:33:25 +02:00
doc draw_graph_points() split big XDrawLines requests into smaller chunks to handle raw files with > 4M points 2023-04-14 15:41:00 +02:00
scconfig change preprocessor defined(HAS_CAIRO) to HAS_CAIRO==1 2023-04-09 15:36:06 +02:00
src print_spice_subckt_nodes(): remove closing bracket in case of tcleval(...) failure 2023-04-17 10:33:45 +02:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library updates to ngspice/comp_65nm.* 2023-04-13 12:10:04 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions