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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 710e694f40 merge_file(): handle generators so generated schematics (pcells) can be merged into an existing schematic 2023-04-28 17:34:04 +02:00
XSchemWin Correct menu accelerator shown for "merge" function (b key) 2023-04-11 09:33:25 +02:00
doc doc updates (sch/sym generators, aka pcells) 2023-04-28 12:03:56 +02:00
scconfig change preprocessor defined(HAS_CAIRO) to HAS_CAIRO==1 2023-04-09 15:36:06 +02:00
src merge_file(): handle generators so generated schematics (pcells) can be merged into an existing schematic 2023-04-28 17:34:04 +02:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions