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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 626f2729ce remove used_symbols feature (may fail in some hierarchical situations) 2023-05-10 10:13:38 +02:00
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XSchemWin mosgen has been changed to mosgen.tcl 2023-05-08 23:15:58 +02:00
doc istances with *_ignore=true attribute will be drawn greyed out in schematics in the corresponding netlisting mode; command in Properties menu to toggle this attribute on selected instances 2023-05-10 03:13:13 +02:00
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tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library use symbol_ignore=true attribute on some objects in mos_power_ampli.sch, so they disappear in poweramp_lcc.sch 2023-05-10 04:49:32 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions