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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,306 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
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Stefan Frederik 5fe2f1586b refactor str_hash_* and int_hash_* functions 2022-10-05 01:18:45 +02:00
XSchemWin (Joanne) update to be clearer on how to compile xschem (from scratch vs using XSchemWin.sln) on Windows using VS2022. font.sch micro edits 2022-09-28 11:33:48 +02:00
doc doc updates about {verilog,vhdl,spice}_sym_def, fix regression (possible crash) in verilog_block_netlist (thanks to Joanne), fix regression (wrong verilog test netlist) in print_verilog_primitive() (thanks to Joanne) 2022-10-04 00:37:09 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src refactor str_hash_* and int_hash_* functions 2022-10-05 01:18:45 +02:00
tests update xschemtest.tcl 2022-10-04 00:39:48 +02:00
xschem_library refactor str_hash_* and int_hash_* functions 2022-10-05 01:18:45 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions