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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 5cc1f04588 move.c: removed redundant drawing, now all areas are restored from pixmap by draw(). Postscript print: addition of (limited) unicode characters (0xC2 and 0xC3 2-byte sets are recoded to fit into the 256 slot postscript core font dictionaries). When editing multiple text objects with "preserve unchanged attrs" set do not change individual text dimensions. 2021-01-07 04:33:19 +01:00
XSchemWin added new examples to windows install [Joanne] 2020-12-30 12:16:34 +01:00
doc fix uncommented line (xschem start window) in xschemrc and link in doc main html page 2021-01-05 03:53:55 +01:00
scconfig add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports 2021-01-06 00:12:04 +01:00
src move.c: removed redundant drawing, now all areas are restored from pixmap by draw(). Postscript print: addition of (limited) unicode characters (0xC2 and 0xC3 2-byte sets are recoded to fit into the 256 slot postscript core font dictionaries). When editing multiple text objects with "preserve unchanged attrs" set do not change individual text dimensions. 2021-01-07 04:33:19 +01:00
tests redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
xschem_library add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports 2021-01-06 00:12:04 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli 2020-12-17 03:48:34 +01:00
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LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
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config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions