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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 4c43e77818 eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded) 2022-10-24 17:28:39 +02:00
XSchemWin improved find_file proc, added match_file 2022-10-18 00:02:10 +02:00
doc doc updates (graph resize, commands to select/resize objects) 2022-10-23 23:55:09 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src do not trigger modify status if enter_text dialog box closed with no changes 2022-10-24 16:07:13 +02:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded) 2022-10-24 17:28:39 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions