A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Rafmag Cabrera 4814d10a67
Merge branch 'StefanSchippers:master' into master
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XSchemWin fflush() all stdio buffers before calling fork(). End child processes with _exit() instead of exit() to avoid double fflushing in parent i/o streams 2023-01-19 02:46:45 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions